Ansys achieved certification of its state-of-the-art multiphysics signoff solution for TSMC’s most advanced 3nm process technology. This enables mutual customers to satisfy key power, thermal and reliability requirements for the world’s largest AI/ML, 5G, HPC, networking and autonomous vehicle chips.
Achieving power integrity and electromigration (EM) reliability for 3nm process technology remains a challenging signoff milestone. Traditional discrete EM and voltage-drop methodologies are no longer sufficient for signoff of the 3nm process, which integrates billions of transistors and delivers tremendous power and performance on a single die. 3nm requires a comprehensive power integrity, thermal integrity, and reliability analysis platform that Ansys delivers with Ansys RedHawk-SC and Ansys Totem.
The certification of RedHawk-SC for TSMC N3 process encompasses power network extraction, power integrity and reliability, signal EM, thermal reliability analysis for self-heat, thermal-aware EM and statistical EM budgeting. Redhawk-SC will analyze huge 3nm network designs by leveraging the elastic compute, big-data analytics and high capacity of its underlying Ansys SeaScape infrastructure. Totem is similarly certified for transistor-level custom designs.
“We’re pleased with the result of our latest collaboration with Ansys in providing multiphysics design solutions on TSMC’s most advanced 3nm process technology to help our mutual customers address the design complexity and technical challenges,” said Suk Lee, Senior Director of the Design Infrastructure Management Division at TSMC. “This joint effort combining Ansys’ cutting-edge solution and TSMC’s advanced process helps our customers unleash their silicon innovations for next-generation 3nm chipsets that will power many applications.”
“The latest certification continues Ansys’ close collaboration with TSMC to pioneer solutions for our joint customers,” said John Lee, vice president and general manager, Ansys. “Ansys’ broad range of multiphysics simulation and analysis technologies — from chip-level to system-level — makes us ideally placed to enable larger designs with lower power requirements for AI/ML, 5G, HPC, networking and image processing applications.”