CAES Wins Contracts for Development of Next-Generation, Octa-Core, User-Selectable CPU for Space

CAES has won multiple contracts with the European Space Agency (ESA) for the development of the GR765 System-on-Chip (SOC), the first user selectable CPU for space. This next-generation, radiation-hardened device will allow users to select between the LEON5 SPARC V8 or NOEL-V RISC-V RV64 processor cores.

CAES previously received funding from the Swedish National Space Agency (SNSA) within ESA’s General Support Technology Program (GSTP) for the preliminary GR765 system requirement development. In parallel, a demo chip with LEON5 and NOEL-V fault tolerant cores has been fabricated on STMicroelectronics’ 28nm FDSOI technology. The new incremental Advanced Research in Telecommunications Systems (ARTES) and Technology Development Element (TDE) program contracts will enable CAES to move forward with the GR765 prototype development and manufacturing on this technology. 

The official contract signing took place at the International Astronautical Congress (IAC) in the Swedish pavilion, September 22, 2022, in Paris, France. The director of Telecommunications and Integrated Applications at ESA, Elodie Viau and CAES Gaisler Product’s general manager, Sandi Habinc were in attendance. 

“ESA is proud to collaborate with CAES in developing this next generation of data processing technology which is instrumental to build intelligent, powerful and secure systems in space. Our cooperation will enhance Europe’s capacity to launch and conduct its ambitious future missions and puts us in a pole position to advance the global technological standard for data processing in space,” said Elodie Viau, director of Telecommunications and Integrated Applications at ESA. 

“The CAES GR765 responds to the ever-increasing demands of telecommunication payload data processing, but also benefits a broad range of other mission-critical applications such as on-board computing,” said Michael Harverson, head of the Space Segment Section at ESA. 

“CAES is excited to announce the first user-selectable CPU for space. We are providing our customers with options to select the best architecture based on their requirements, while meeting the space industry’s future needs for more computing and a seamless ecosystem as well as addressing Size, Weight and Power (SWaP),” said Mike Elias, senior vice president and general manager, Space Systems Division, CAES. 

CAES will work closely with STMicroelectronics, a leading European semiconductor company, on product manufacturing and qualifications for the GR765. “We are proud to team with CAES on their next-generation microprocessors for space. The combination of proven SPARC and RISC-V technology with 28nm FDSOI’s technology capability and maturity for space is a perfect match,” said Francois Martin, Head of Space & Defense ASICs Business Development, Microcontroller & Digital Group, STMicroelectronics. “In addition to silicon manufacturing, ST provides HiRel product manufacturing and qualification through its trusted supply chain in its factories in Crolles and Rennes, France.” 

The GR765 System-On-Chip will offer greater flexibility and functionality while providing the higher processing and bandwidth needed for future space applications. It will also allow the user to reuse legacy LEON SPARC software or develop new software for the NOEL-V RISC-V architecture, providing the option to leverage state-of-the-art software developed in other industries. 

Based on the radiation test on the demo chip, CAES estimates the SEU tolerance for the GR765 product to be at least five times harder than the current radiation hardened processors. CAES will implement its legacy approach to fault tolerance, allowing software to transparently continue execution in presence of correctable errors, as well as extending fault tolerance to peripherals and software libraries.

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